Semiconductor memory circuits are being developed with greater densities, primarily as a result of decreasing circuit geometries. For dynamic random access memories the greater density also reduces the quantity of charge which can be stored within each memory cell. The close spacing of circuit elements further tends to increase the electrical effect of the operation of one circuit upon another, particularly through capacitive coupling. There is also a trend to design semiconductor memories to operate from a single 5.0 volt supply. Each of these design factors tends to reduce the signal margin available for reading the voltage state stored in the memory cells of a dynamic random access memory. When a selected memory cell is coupled to a bit line, the change in voltage on the bit line can be very small. The coupling of electrical noise from other circuit elements within the semiconductor memory can change the amplitude of the signal on the bit lines such that there is insufficient signal level to correctly read the state of the memory cell. Clock circuits in particular can generate noise that can be propagated to the bit lines.
In view of these problems there exists a need for a design of circuit elements in a semiconductor memory to reduce the impact of electrical noise which is coupled into the bit lines from other circuits, such as clock generators, which operate on the same semiconductor substrate.